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Features
* High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture
- 120 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation Non-volatile Program and Data Memories - 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny24/44/84) Endurance: 10,000 Write/Erase Cycles - 128/256/512 Bytes In-System Programmable EEPROM (ATtiny24/44/84) Endurance: 100,000 Write/Erase Cycles - 128/256/512 Bytes Internal SRAM (ATtiny24/44/84) - Programming Lock for Self-Programming Flash Program and EEPROM Data Security Peripheral Features - Two Timer/Counters, 8- and 16-bit counters with two PWM Channels on both - 10-bit ADC 8 single-ended channels 12 differential ADC channel pairs with programmable gain (1x, 20x) Temperature Measurement - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator - Universal Serial Interface Special Microcontroller Features - debugWIRE On-chip Debug System - In-System Programmable via SPI Port - External and Internal Interrupt Sources - Pin Change Interrupt on 12 pins - Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes - Enhanced Power-on Reset Circuit - Programmable Brown-out Detection Circuit - Internal Calibrated Oscillator - On-chip Temperature Sensor I/O and Packages - 14-pin SOIC, PDIP and 20-pin QFN/MLF: Twelve Programmable I/O Lines Operating Voltage: - 1.8 - 5.5V for ATtiny24V/44V/84V - 2.7 - 5.5V for ATtiny24/44/84 Speed Grade - ATtiny24V/44V/84V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V - ATtiny24/44/84: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption - Active Mode: 1 MHz, 1.8V: 380 A - Power-down Mode: 1.8V: 100 nA
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8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny24/44/84 Preliminary Summary
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Rev. 8006FS-AVR-02/07
1. Pin Configurations
Figure 1-1. Pinout ATtiny24/44/84
PDIP/SOIC
VCC (PCINT8/XTAL1/CLKI) PB0 (PCINT9/XTAL2) PB1 (PCINT11/RESET/dW) PB3 (PCINT10/INT0/OC0A/CKOUT) PB2 (PCINT7/ICP/OC0B/ADC7) PA7 (PCINT6/OC1A/SDA/MOSI/ADC6) PA6 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND PA0 (ADC0/AREF/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/T0/PCINT3) PA4 (ADC4/USCK/SCL/T1/PCINT4) PA5 (ADC5/DO/MISO/OC1B/PCINT5)
QFN/MLF
Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/ADC6) Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5) PA7 (PCINT7/ICP/OC0B/ADC7) PB2 (PCINT10/INT0/OC0A/CKOUT) PB3 (PCINT11/RESET/dW) PB1 (PCINT9/XTAL2) PB0 (PCINT8/XTAL1/CLKI) PA5 DNC DNC DNC PA6 NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect
1.1
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
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DNC DNC GND VCC DNC
6 7 8 9 10
(ADC4/USCK/SCL/T1/PCINT4) PA4 (ADC3/T0/PCINT3) PA3 (ADC2/AIN1/PCINT2) PA2 (ADC1/AIN0/PCINT1) PA1 (ADC0/AREF/PCINT0) PA0
1 2 3 4 5
20 19 18 17 16
15 14 13 12 11
ATtiny24/44/84
2. Overview
The ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
VCC 8-BIT DATABUS INTERNAL OSCILLATOR GND
PROGRAM COUNTER STACK POINTER
Block Diagram
INTERNAL CALIBRATED OSCILLATOR
WATCHDOG TIMER MCU CONTROL REGISTER
TIMING AND CONTROL
PROGRAM FLASH
SRAM
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
X Y Z
MCU STATUS REGISTER TIMER/ COUNTER0 TIMER/ COUNTER1
INSTRUCTION DECODER
CONTROL LINES
ALU
STATUS REGISTER
INTERRUPT UNIT
PROGRAMMING LOGIC
ISP INTERFACE
EEPROM
OSCILLATORS
ANALOG COMPARATOR
DATA REGISTER PORT A
DATA DIR. REG.PORT A
ADC
DATA REGISTER PORT B
DATA DIR. REG.PORT B
+ -
PORT A DRIVERS
PORT B DRIVERS
PA7-PA0
PB3-PB0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
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registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny24/44/84 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, a 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal Oscillator, internal calibrated oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured ng Atmel's high density non-volatile memory technology. The Onchip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny24/44/84 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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ATtiny24/44/84
2.2
2.2.1
Pin Descriptions
VCC Supply voltage.
2.2.2
GND Ground.
2.2.3
Port B (PB3...PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (`0') RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny24/44/84 as listed on Section 12.3 "Alternate Port Functions" on page 61.
2.2.4
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 22-3 on page 183. Shorter pulses are not guaranteed to generate a reset.
2.2.5
Port A (PA7...PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in "Alternate Port Functions" on page 61
3. Resources
A comprehensive set of development tools, drivers and application notes, and datasheets are available for download on http://www.atmel.com/avr.
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4. Register Summary
Address
0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31)) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Name
SREG SPH SPL OCR0B GIMSK GIFR TIMSK0 TIFR0 SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL TCCR0A TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL DWDR CLKPR ICR1H ICR1L GTCCR TCCR1C WDTCSR PCMSK1 EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB GPIOR2 GPIOR1 GPIOR0 PCMSK0 Reserved USIBR USIDR USISR USICR TIMSK1 TIFR1 Reserved Reserved ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Reserved DIDR0 PRR
Bit 7
I - SP7 - - - - - - FOC0A CAL7 COM0A1 COM1A1 ICNC1
Bit 6
T - SP6 INT0 INTF0 - - - PUD - FOC0B CAL6 COM0A0 COM1A0 ICES1
Bit 5
H -
Bit 4
S -
Bit 3
V -
Bit 2
N -
Bit 1
Z SP9 SP1 - - OCIE0A OCF0A PGERS ISC01 EXTRF CS01 CAL1 WGM01 WGM11
Bit 0
C SP8 SP0 - - TOIE0 TOV0 SPMEN ISC00 PORF CS00 CAL0 WGM00 WGM10 CS10
Page
Page 9 Page 12 Page 12 Page 89 Page 53 Page 54 Page 90 Page 90 Page 163 Page 89 Page 53 Page 46 Page 88 Page 89 Page 33 Page 85 Page 114 Page 116 Page 118 Page 118 Page 118 Page 118 Page 118 Page 118 Page 159
SP5 SP4 SP3 SP2 Timer/Counter0 - Output Compare Register B PCIE1 PCIF1 - - - PCIE0 PCIF0 - - - - - - - - OCIE0B OCF0B
CTPB RFLB PGWRT Timer/Counter0 - Output Compare Register A SM1 - - CAL4 COM0B0 COM1B0 WGM13 SM0 WDRF WGM02 CAL3 - - WGM12 CS12 - BORF CS02 CAL2
SE - - CAL5 COM0B1 COM1B1 -
Timer/Counter0
CS11
Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Compare Register A High Byte Timer/Counter1 - Compare Register A Low Byte Timer/Counter1 - Compare Register B High Byte Timer/Counter1 - Compare Register B Low Byte DWDR[7:0] CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte TSM FOC1A WDIF - - EEAR7 - PORTA7 DDA7 PINA7 - - - - FOC1B WDIE - - EEAR6 - PORTA6 DDA6 PINA6 - - - - - WDP3 - - EEAR5 EEPM1 PORTA5 DDA5 PINA5 - - - - - WDCE - - EEAR4 EEPM0 PORTA4 DDA4 PINA4 - - - - - WDE PCINT11 - EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 - - WDP2 PCINT10 - EEAR2 EEMPE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 - - WDP1 PCINT9 - EEAR1 EEPE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PSR10 - WDP0 PCINT8 EEAR8 EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0
Page 33 Page 119 Page 119 Page 122 Page 117 Page 46 Page 54 Page 23 Page 23 Page 23 Page 23 Page 72 Page 72 Page 72 Page 72 Page 72 Page 73 Page 25 Page 25 Page 25
EEPROM Data Register
General Purpose I/O Register 2 General Purpose I/O Register 1 General Purpose I/O Register 0 PCINT7 PCINT6 PCINT5 PCINT4 - USI Buffer Register USI Data Register USISIF USISIE - - USIOIF USIOIE - - USIPF USIWM1 ICIE1 ICF1 USIDC USIWM0 - - - - ACD REFS1 ADEN ACBG REFS0 ADSC ACO MUX5 ADATE ACI MUX4 ADIF ACIE MUX3 ADIE ACIC MUX2 ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 USICNT3 USICS1 - - USICNT2 USICS0 OCIE1B OCF1B USICNT1 USICLK OCIE1A OCF1A USICNT0 USITC TOIE1 TOV1 PCINT3 PCINT2 PCINT1 PCINT0
Page 55 Page 131 Page 131 Page 131 Page 132 Page 119 Page 120
Page 137 Page 151 Page 154 Page 155 Page 155
ADC Data Register High Byte ADC Data Register Low Byte BIN ADC7D - ACME ADC6D - - ADC5D - ADLAR - ADC4D - ADC3D PRTIM1 ADC2D PRTIM0 ADC1D PRUSI ADC0D PRADC - ADTS2 ADTS1 ADTS0
Page 156 Page 138,Page 157 Page 36
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Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
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5. Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers
Description
Rd Rd + Rr
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1
ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0
BRANCH INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
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Mnemonics
ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (z) R1:R0 Rd P P Rr STACK Rr Rd STACK None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 2 2 1 1 1 N/A 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3
Operands
Rd Rd Rd Rd s s Rr, b Rd, b
Description
Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
Operation
Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0
Flags
Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H
#Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MCU CONTROL INSTRUCTIONS
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6. Ordering Information
6.1 ATtiny24
Speed (MHz) 10 Power Supply 1.8 - 5.5V Ordering Code(1) ATtiny24V-10SSU ATtiny24V-10PU ATtiny24V-10MU ATtiny24-20SSU ATtiny24-20PU ATtiny24-20MU Package(2) 14S1 14P3 20M1 14S1 14P3 20M1 Operational Range Industrial (-40C to 85C)
20 Notes:
2.7 - 5.5V
Industrial (-40C to 85C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
Package Type 14S1 14P3 20M1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
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ATtiny24/44/84
6.2 ATTINY44
Speed (MHz) 10 Power Supply 1.8 - 5.5V Ordering Code(1) ATTINY44V-10SSU ATTINY44V-10PU ATTINY44V-10MU ATTINY44-20SSU ATTINY44-20PU ATTINY44-20MU Package(2) 14S1 14P3 20M1 14S1 14P3 20M1 Operational Range Industrial (-40C to 85C)
20 Notes:
2.7 - 5.5V
Industrial (-40C to 85C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
Package Type 14S1 14P3 20M1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
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6.3
ATtiny84
Speed (MHz) 10 20 Power Supply 1.8 - 5.5V 2.7 - 5.5V Ordering Code(1) ATtiny84V-10PU ATtiny84V-10MU ATtiny84-20PU ATtiny84-20MU Package(2) 14P3 20M1 14P3 20M1 Operational Range Industrial (-40C to 85C) Industrial (-40C to 85C)
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
Package Type 14S1 14P3 20M1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
12
ATtiny24/44/84
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7. Packaging Information
7.1 20M1
D
1 Pin 1 ID 2 3
E
SIDE VIEW
TOP VIEW A2 D2 A1 A
1 Pin #1 Notch (0.20 R) 2 3
0.08
C
E2
SYMBOL A A1
COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.70 - NOM 0.75 0.01 0.20 REF 0.18 0.23 4.00 BSC 2.45 2.60 4.00 BSC 2.45 2.60 0.50 BSC 0.35 0.40 0.55 2.75 2.75 0.30 MAX 0.80 0.05 NOTE
b
L e BOTTOM VIEW
A2 b D D2 E E2 e
Note:
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
L
10/27/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 20M1 REV. A
R
13
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7.2
14P3
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eC eB
SYMBOL A A1 D E E1 B Notes: 1. This package conforms to JEDEC reference MS-001, Variation AA. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 18.669 7.620 6.096 0.356 1.143 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 19.685 8.255 7.112 0.559 1.778 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE
2.540 TYP
11/02/05 2325 Orchard Parkway San Jose, CA 95131 TITLE 14P3, 14-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 14P3 REV. A
R
14
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ATtiny24/44/84
7.3 14S1
1
E E H
N
L
Top View
End View
e A1
b
SYMBOL
COMMON DIMENSIONS (Unit of Measure = mm/inches) MIN NOM MAX NOTE
A
1.35/0.0532 0.1/.0040 0.33/0.0130 8.55/0.3367 3.8/0.1497 5.8/0.2284 0.41/0.0160
- - - - - - - 1.27/0.050 BSC
1.75/0.0688 0.25/0.0098 0.5/0.0200 5 8.74/0.3444 3.99/0.1574 6.19/0.2440 1.27/0.0500 4 2 3
A
A1 b
D
D E
Side View
H L e
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. L is the length of the terminal for soldering to a substrate. 5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side.
2/5/02 TITLE
R
DRAWING NO. 14S1, 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14S1
2325 Orchard Parkway San Jose, CA 95131
REV. A
15
8006FS-AVR-02/07
8. Errata
The revision letter in this section refers to the revision of the ATtiny24/44/84 device.
8.1
8.1.1
ATtiny24
Rev. D No known errata.
8.1.2
Rev. C * Reading EEPROM when system clock frequency is below 900 kHz may not work 1. Reading EEPROM when system clock frequency is below 900 kHz may not work Reading data from the EEPROM at system clock frequency below 900 kHz may result in wrong data read. Problem Fix/Work around Avoid using the EEPROM at clock frequency below 900 kHz.
8.1.3
Rev. B * EEPROM read from application code does not work in Lock Bit Mode 3 * Reading EEPROM when system clock frequency is below 900 kHz may not work 1. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Work around Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 2. Reading EEPROM when system clock frequency is below 900 kHz may not work Reading data from the EEPROM at system clock frequency below 900 kHz may result in wrong data read. Problem Fix/Work around Avoid using the EEPROM at clock frequency below 900 kHz.
8.1.4
Rev. A Not sampled.
16
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8.2
8.2.1
ATTINY44
Rev. B No known errata.
8.2.2
Rev. A * Reading EEPROM when system clock frequency is below 900 kHz may not work 1. Reading EEPROM when system clock frequency is below 900 kHz may not work Reading data from the EEPROM at system clock frequency below 900 kHz may result in wrong data read. Problem Fix/Work around Avoid using the EEPROM at clock frequency below 900 kHz.
17
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8.3
8.3.1
ATtiny84
Rev. A No known errata.
18
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9. Datasheet Revision History
9.1 Rev F. 02/07
1. 2.
3. 4. 5. 6. 7. 8. 9.
Updated Figure 1-1 on page 2, Figure 9-7 on page 45, Figure 22-5 on page 187. Updated Table 10-1 on page 50, Table 12-7 on page 69, Table 13-2 on page 85, Table 13-3 on page 85, Table 13-5 on page 86, Table 13-6 on page 86, Table 13-7 on page 87, Table 13-8 on page 87, Table 22-6 on page 185, Table 22-8 on page 187. Updated table references in "TCCR0A - Timer/Counter Control Register A" on page 85. Updated Port B, Bit 0 functions in "Alternate Functions of Port B" on page 69. Updated WDTCR bit name to WDTCSR in assembly code examples. Updated bit5 name in Section 14.11.9 on page 120. Updated bit5 in Section 14.11.9 on page 120. Updated "SPI Master Operation Example" on page 126. Updated step 5 in "Enter High-voltage Serial Programming Mode" on page 174.
9.2
Rev E. 09/06
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
All characterization data is moved to "Electrical Characteristics" on page 180. All Register Descriptions are gathered up in separate sections in the end of each chapter. Updated "System Control and Reset" on page 40. Updated Table 13-3 on page 85, Table 13-6 on page 86, Table 13-8 on page 87, Table 14-2 on page 114 and Table 14-4 on page 116. Updated "Fast PWM Mode" on page 105. Updated Figure 14-7 on page 106 and Figure 18-1 on page 140. Updated "Analog Comparator Multiplexed Input" on page 135. Added note in Table 21-11 on page 171. Updated "Electrical Characteristics" on page 180. Updated "Typical Characteristics - Preliminary Data" on page 188.
9.3
Rev D. 08/06
1. 2. 3. 4. 5. 6.
Updated "Calibrated Internal RC Oscillator" on page 30. Updated "Oscillator Calibration Register - OSCCAL" on page 33. Added Table 22-1 on page 182. Updated code examples in "SPI Master Operation Example" on page 126. Updated code examples in "SPI Slave Operation Example" on page 127. Updated "Signature Bytes" on page 167. 19
8006FS-AVR-02/07
9.4
Rev C. 07/06
1. 2. 3. 4.
Updated Features in "USI - Universal Serial Interface" on page 123. Added "Clock speed considerations" on page 130. Updated Bit description in "ADMUX - ADC Multiplexer Selection Register" on page 151. Added note to Table 20-1 on page 163.
9.5
Rev B. 05/06
1. 2. 3.
4. 5. 6. 7. 8. 9.
Updated "Default Clock Source" on page 27 Updated "Power Reduction Register" on page 36. Updated Table 22-3 on page 183, Table 9-4 on page 42, Table 18-3 on page 151, Table 21-5 on page 167, Table 21-11 on page 171, Table 21-15 on page 177, Table 22-6 on page 185. Updated Features in "Analog to Digital Converter" on page 139. Updated Operation in "Analog to Digital Converter" on page 139. Updated "Temperature Measurement" on page 150. Updated DC Characteristics in "Electrical Characteristics" on page 180. Updated "Typical Characteristics - Preliminary Data" on page 188. Updated "Errata" on page 223.
9.6
Rev A. 12/05
Initial revision.
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ATtiny24/44/84
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Atmel Corporation
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8006FS-AVR-02/07

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